AMD64: amd64.org_asm-include_fixes4yasm.200603221217.patch

aa64_crx.inc

@@ -17 +17 @@
 %define                 CR3_AVL64               (BITS_QWORD - BITS_CR3_AVL64)
 
 %if BITS_AA64_PHYSICAL > CR3_AVL64
- %error due to the AVL64 bits CR3 can't hold that many base address bits
+ %error "due to the AVL64 bits CR3 can't hold that many base address bits"
 %endif
 
 %define                 CR3_BAS_PML4            12

aa64_desc.inc

@@ -272 +272 @@
                         %elifidni %3,GATE
                          %ifidni %4,CALL
                           %ifidn %1,IDT64
-                           %error 64 bit call gate descriptors can't reside in the IDT
+                           %error "64 bit call gate descriptors can't reside in the IDT"
                           %endif
                           istruc MEM_DESC_GATE_CALL64
                            at MEM_DESC_GATE_CALL64.OFF_15_0,    dw ((%6) & MAX_WORD)

aa64_opc_rm32.inc

@@ -19 +19 @@
 
 %define                 RM32_REG_R8B            8
 %define                 RM32_REG_R9B            9
-%define                 RM32_REG_R11B           10
+%define                 RM32_REG_R10B           10
 %define                 RM32_REG_R11B           11
 %define                 RM32_REG_R12B           12
 %define                 RM32_REG_R13B           13
@@ -28 +28 @@
 
 %define                 RM32_REG_R8W            8
 %define                 RM32_REG_R9W            9
-%define                 RM32_REG_R11W           10
+%define                 RM32_REG_R10W           10
 %define                 RM32_REG_R11W           11
 %define                 RM32_REG_R12W           12
 %define                 RM32_REG_R13W           13
@@ -37 +37 @@
 
 %define                 RM32_REG_R8D            8
 %define                 RM32_REG_R9D            9
-%define                 RM32_REG_R11D           10
+%define                 RM32_REG_R10D           10
 %define                 RM32_REG_R11D           11
 %define                 RM32_REG_R12D           12
 %define                 RM32_REG_R13D           13
@@ -46 +46 @@
 
 %define                 RM32_REG_R8             8
 %define                 RM32_REG_R9             9
-%define                 RM32_REG_R11            10
+%define                 RM32_REG_R10            10
 %define                 RM32_REG_R11            11
 %define                 RM32_REG_R12            12
 %define                 RM32_REG_R13            13

aa64_paging.inc

@@ -36 +36 @@
 %define                 PMLxE_AVL64             (BITS_QWORD - BITS_PMLxE_AVL64)
 
 %if BITS_AA64_PHYSICAL > PMLxE_AVL64
- %error due to the AVL64 bits a PMLxE can't hold that many base address bits
+ %error "due to the AVL64 bits a PMLxE can't hold that many base address bits"
 %endif
 
 %define                 MASK_PMLxE_AVL64        (((1 << BITS_PMLxE_AVL64) - 1) << PMLxE_AVL64)
@@ -186 +186 @@
 %define                 MASK_PDE_4KB_BAS        (((1 << (BITS_AA64_PHYSICAL - PDE_4KB_BAS)) - 1) << PDE_4KB_BAS)
 
 %if BITS_AA64_PHYSICAL > 41
- %error the 4 MB PDE can't hold more than 41 page base address bits
+ %error "the 4 MB PDE can't hold more than 41 page base address bits"
 %endif
 
 %define                 MASK_PDE_4MB_BAS_HIGH   (((1 << (BITS_AA64_PHYSICAL - BITS_DWORD)) - 1) << PDE_4MB_BAS_HIGH)

ia32_desc.inc

@@ -425 +425 @@
                         %elifidni %3,SEG
                          %ifidni %4,CODE
                           %ifidn %1,IDT
-                           %error code segment descriptors can't reside in the IDT
+                           %error "code segment descriptors can't reside in the IDT"
                           %endif
                           istruc MEM_DESC_SEG_CODE
                            at MEM_DESC_SEG_CODE.LIM_15_0,       dw (temp1 & MAX_WORD)
@@ -436 +436 @@
                           iend
                          %elifidni %4,DATA
                           %ifidn %1,IDT
-                           %error data segment descriptors can't reside in the IDT
+                           %error "data segment descriptors can't reside in the IDT"
                           %endif
                           %if (temp2 & MASK_AR_SEG_DATA_X) = MASK_AR_SEG_DATA_X
                            %if (temp2 & MASK_AR_SEG_DATA_W) = 0
@@ -478 +478 @@
                         %elifidni %3,GATE
                          %ifidni %4,CALL
                           %ifidn %1,IDT
-                           %error call gate descriptors can't reside in the IDT
+                           %error "call gate descriptors can't reside in the IDT"
                           %endif
                           istruc MEM_DESC_GATE_CALL
                            at MEM_DESC_GATE_CALL.OFF_15_0,      dw ((%6) & MAX_WORD)

ia32_msr.inc

@@ -276 +276 @@
 %define                 MSR_MTRR_PHYS_MASK_n_V          11
 
 %define                 MASK_MSR_MTRR_PHYS_MASK_n_MASK  (((1 << (BITS_IA32_PHYSICAL - MSR_MTRR_PHYS_MASK_n_MASK)) - 1) << MSR_MTRR_PHYS_MASK_n_MASK)
-%define                 MASK_MSR_MTRR_PHYS_MASK_n_V     (MAX_BYTE << MSR_MTRR_PHYS_MASK_n_V)
+%define                 MASK_MSR_MTRR_PHYS_MASK_n_V     (1 << MSR_MTRR_PHYS_MASK_n_V)
 
 ;------------------------------------------------------------------------------
 ;       MCAR MSR bits
@@ -390 +390 @@
 %define                 MSR_APIC_BASE_E                 11
 %define                 MSR_APIC_BASE_BSP               8
 
-%define                 MSR_APIC_BASE_BASE              (((1 << (BITS_IA32_PHYSICAL - MSR_APIC_BASE_BASE)) - 1) << MSR_APIC_BASE_BASE)
+%define                 MASK_MSR_APIC_BASE_BASE         (((1 << (BITS_IA32_PHYSICAL - MSR_APIC_BASE_BASE)) - 1) << MSR_APIC_BASE_BASE)
 %define                 MASK_MSR_APIC_BASE_E            (1 << MSR_APIC_BASE_E)
 %define                 MASK_MSR_APIC_BASE_BSP          (1 << MSR_APIC_BASE_BSP)
 

ia32_paging.inc

@@ -123 +123 @@
 %define                 PDE_4MB_P               PxE_P
 
 %if BITS_IA32_PHYSICAL > 41
- %error the 4 MB PDE can't hold more than 41 page base address bits
+ %error "the 4 MB PDE can't hold more than 41 page base address bits"
 %endif
 
 %define                 MASK_PDE_4MB_BAS        (((1 << (BITS_DWORD - PDE_4MB_BAS)) - 1) << PDE_4MB_BAS)

ia32_tss.inc

@@ -145 +145 @@
 %macro                  CALC_C_IOPB 3           ; port, offset, mask
 
                         %if (%1) < MIN_WORD
-                         %error port can't be negative
+                         %error "port can't be negative"
                         %endif
 
                         %if (%1) > (MAX_WORD + BYTES_DWORD - 1)

asm-includes.

@@ -12 +12 @@
 ;       NASM stuff
 ;------------------------------------------------------------------------------
 
-%locals .
+; not recognized by yasm:
+; %locals .
 
 %define off offset      ; since there is a "seg", using "off" is cleaner
 
@@ -125 +126 @@
 ;------------------------------------------------------------------------------
 
 %macro CHECK_C_STRUC_SIZE 2
- %if %1_size <> (%2)
-  %error structure has unexpected size
- %endif
+;  yasm does not like the "%1_size"
+; %if %1_size <> (%2)
+;  %error structure has unexpected size
+; %endif
 %endmacro
 
 ;------------------------------------------------------------------------------