SSE4 instruction set

[Peter Johnson]

On Sun, 10 Sep 2006, Mathieu Monnier wrote:

> Attached is a patch attempting to add SSE4 instruction set support to yasm. 
> At the moment, I'm not even sure the opcodes generated are correct, I'll 
> only be able to check that during the week. Yet I post the patch now, in 
> order to know whether - at least - I did the thing properly or not.
>
> I had, prior to today, no knowledge whatsoever on how opcodes where 
> generated, nor on yasm source code, so I most probably borked something. So 
> you are more than welcome to comment on the patch structure while I check 
> its validity.

Yes, the patch looks good.  In r1612 (just committed) I moved CPU_64 and 
CPU_Not64 to bits 30 and 31 so you can move your new CPU_SSE4 define to 
bit 27 (actually I found a bug while doing this, as CPU_64 was overlapping 
CPU_EM64T).

As you suggest, I'll wait to commit this until we have a concrete 
reference for the opcodes.  Let us know!

Thanks,
Peter