movdqa/movdqu amd64 glitches

[Peter Johnson]

Thanks for the bug report!

You're correct, the prefix ordering was incorrect.  Originally we
implemented the SSE2 instructions according to Intel's thinking: don't
treat the first byte of those instructions as a prefix.  It turns out that
AMD64 treats them just like other legacy prefixes, which come before the
REX byte.  We had to add a new field to handle this to the x86_bytecode
structure (as well as in x86id.re).

In any case, it's fixed in CVS, and the fix will be in the next release.

Thanks,
Peter Johnson

On Tue, 3 Feb 2004, Henryk Richter wrote:

> I attempted to use the extended xmm8-xmm15 registers for move operations
> but yasm generates the wrong instruction byte order.
>
> example:
>
> movdqa  xmm10, xmm1 ; assembles to    44 66 0f 6f d1 (rexX movdqa
> xmm2,xmm1)
>
> while gnu as outputs   66 44 0f 6f d1 correctly.
>
> I didn't find the swapping flag in x86.re, so I'm kindly asking here
> for a hint.
>